DAC 2010

ASIC Analytic can greatly reduce HDL debug time by thoroughly analyzing your structural HDL, both Verilog and VHDL. This is done by using our flagship product, HDLProbe®. Watch the video below for a quick introduction about why HDLProbe® is so useful.

To learn more about HDLProbe®, the video below is the live presentation given at DAC 2010. It goes into more depth on how HDLProbe® helps you increase productivity by reducing debug time.

We are currently analyzing HDL from several IP vendors and we invite you to participate! You benefit by receiving free analysis while we use your HDL to complete our code.

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