HDL Probe(TM):

• Setup - NONE!
  • NO Tech Files
  • NO GUI
  • NO Config Files
  • NO Constraints
  • NO Training
  • NO ...
• Input is Structural HDL ( Verilog or VHDL )
• Output
  • Prioritized list of all non-standard circuit topologies
  • All circuit errors and their sources
  • Clean formatted HDL
  • HDL Test Bench
• Environment
  • Network attached box for maximum performance
  • Web based compute cloud for minimal IT support

Advantages:

• Increases ASIC quality and reduces time to market through innovative algorithms based on many years of design experience
• Catches design flaws, inefficiencies and anomalies that currently available tools miss
• Provides detailed summary of your design to confirm design intent is intact